1. Field of the Invention
The present invention relates to a high-voltage semiconductor device and a method for manufacturing the same, and more particularly, to a high-voltage semiconductor device capable of applying a bulk bias to a high-voltage NMOS transistor included in the high-voltage semiconductor device and a method for manufacturing the same.
2. Discussion of the Related Art
Generally, semiconductor devices use a low voltage of 3.3V or less as a supply voltage, in order to achieve a reduction in power consumption and to secure a desired reliability. In a certain system, such a semiconductor device is connected with peripheral devices, which may use a high voltage of 5V or more. For this reason, the semiconductor device must be equipped with a high-voltage transistor to support a high input voltage supplied from outside of the system.
Such a high-voltage transistor typically has a MOS transistor structure, namely, the same structure as the low voltage transistor. The high-voltage transistor is formed simultaneously with the low voltage transistor, through a series of fabrication processes.
Hereinafter, a conventional high-voltage semiconductor device including a high-voltage transistor and a method for manufacturing the same will be described.
FIG. 1 is a sectional view illustrating a conventional high-voltage semiconductor device.
In order to manufacture the conventional high-voltage semiconductor device, a P type well 12 is first formed in a P type semiconductor substrate 10, as shown in FIG. 1. A mask (not shown) is then formed on the semiconductor substrate 10 such that isolation regions are exposed through the mask. The substrate regions exposed through the mask are then etched to form trenches. An insulating film is subsequently deposited to fill the trenches.
Thereafter, a chemical mechanical polishing (CMP) process is carried out such that the insulating film is left only in the trenches, to form isolation films 16.
Subsequently, an oxide film and a polysilicon film are sequentially formed over the resultant surface of the semiconductor substrate 10. The oxide film and polysilicon film are then patterned, to form a gate insulating film 18 and a gate electrode 20 on the semiconductor substrate 10 in a desired region.
N type low-concentration impurity ions are then implanted in the semiconductor substrate 10, to form lightly-doped N type impurity regions 14.
Thereafter, an insulating film for spacers, for example, a nitride film, is deposited over the resultant surface of the semiconductor substrate 10 including the gate electrode 20. The insulating film is then etched back, to form sidewall spacers 22 at side surfaces of the gate electrode 20 and gate insulating film 18.
In the semiconductor substrate 10 formed with the lightly-doped N type impurity region 14, high concentration impurity ions having the same conductivity as the lightly-doped N type impurity regions 14 are then implanted, to form heavily-doped N type impurity regions 24. Thus, source/drain electrodes are formed by the lightly-doped N type impurity regions 14 and heavily-doped N type impurity regions 24.
In the semiconductor device having the above-mentioned structure, it may be impossible to apply a bulk bias to the high-voltage NMOS transistor during normal operations. That is, the high-voltage NMOS transistor may have a problem in that it may not work when a plus bias is applied to the high-voltage NMOS transistor because both the well of the high-voltage NMOS transistor and the semiconductor substrate have a P type conductivity. For this reason, the semiconductor device may increase the complexity of an LCD driver IC (LDI) chip design and cause an increased chip size.